/*
 * Copyright     :  Copyright (C) 2021, Huawei Technologies Co. Ltd.
 * File name     :  pcie5_pcs_addr_define.h
 * Project line  :  Platform And Key Technologies Development
 * Department    :  CAD Development Department
 * Version       :  1.0
 * Date          :
 * Description   :  The description of HIPCIECTRL30V200 project
 * Others        :  Generated automatically by nManager V5.1
 * History       :  2021/01/07 09:57:53 Create file
 */

#ifndef PCIE5_PCS_ADDR_DEFINE_H
#define PCIE5_PCS_ADDR_DEFINE_H

/* HIPCIEC50_PCS_GLB_REG Base address of Module's Register */
#define CSR_HIPCIEC50_PCS_GLB_REG_BASE (0x5A000)

/* **************************************************************************** */
/*                      HIPCIEC50_PCS_GLB_REG Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_HIPCIEC50_PCS_GLB_REG_RATE_CHANGE_TIME_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x0) /* rate change time config. */
#define CSR_HIPCIEC50_PCS_GLB_REG_POWER_CHANGE_1US_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x4) /* power change time config. */
#define CSR_HIPCIEC50_PCS_GLB_REG_CFG_A_LINE_ERR_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x8) /* Error inject line-A high 31bit */
#define CSR_HIPCIEC50_PCS_GLB_REG_CFG_B_LINE_ERR_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0xC) /* Error inject line-B high 31bit */
#define CSR_HIPCIEC50_PCS_GLB_REG_CFG_C_LINE_ERR_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x10) /* Error inject line-C high 31bit */
#define CSR_HIPCIEC50_PCS_GLB_REG_PWR_STAY_TIME_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x18)   /* power stay mini-time */
#define CSR_HIPCIEC50_PCS_GLB_REG_TRACE_DATA_MASK_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x20) /* Trace trigger mask */
#define CSR_HIPCIEC50_PCS_GLB_REG_APB_WR_NUM_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x24)      /* apb write counter */
#define CSR_HIPCIEC50_PCS_GLB_REG_M_PCS_IN18_CFG_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x28) /* pipe selection and bist data */
#define CSR_HIPCIEC50_PCS_GLB_REG_CFG_TRACE_PORT0_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x2C) /* trace0 config. */
#define CSR_HIPCIEC50_PCS_GLB_REG_M_PCS_EQEVAL_CFG_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x30) /* power change time and eqeval enable */
#define CSR_HIPCIEC50_PCS_GLB_REG_ELBUF_EMPTY_PARA_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x34) /* elbuf empty line */
#define CSR_HIPCIEC50_PCS_GLB_REG_RECDET_TIMEOUT_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x38)   /* receive detect time */
#define CSR_HIPCIEC50_PCS_GLB_REG_RECDET_INTERVAL_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x3C) /* receive detect interval time */
#define CSR_HIPCIEC50_PCS_GLB_REG_RATE_TIME_OUT_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x40) /* rate change timeout time */
#define CSR_HIPCIEC50_PCS_GLB_REG_POWER_CHANGE_TIME_OUT_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x44) /* power change timeout time */
#define CSR_HIPCIEC50_PCS_GLB_REG_EQEVAL_TIMEOUT_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x48) /* eqeval timeout time */
#define CSR_HIPCIEC50_PCS_GLB_REG_RX_ELECIDLE_PROTECT_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x54) /* elbuf low latency mode */
#define CSR_HIPCIEC50_PCS_GLB_REG_PCIE_PCS_ECO_RSV0_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x58) /* eco register0 */
#define CSR_HIPCIEC50_PCS_GLB_REG_PCIE_PCS_ECO_RSV1_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x5C) /* eco register1 */
#define CSR_HIPCIEC50_PCS_GLB_REG_PCIE_PCS_ECO_RSV2_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x60) /* eco register2 */
#define CSR_HIPCIEC50_PCS_GLB_REG_PCIE_PCS_ECO_RSV3_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x64) /* eco register3 */
#define CSR_HIPCIEC50_PCS_GLB_REG_PWR_CHGE_60US_TIMEOUT_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x68) /* power change time config and ske remove param */
#define CSR_HIPCIEC50_PCS_GLB_REG_TRACE_DATA_PORT0_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x84)  /* Trace data out */
#define CSR_HIPCIEC50_PCS_GLB_REG_CFG_TRACE_PORT4_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x88)   /* trace4 config. */
#define CSR_HIPCIEC50_PCS_GLB_REG_CFG_TRACE_PORT8_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x8C)   /* trace8 config. */
#define CSR_HIPCIEC50_PCS_GLB_REG_CFG_TRACE_PORT12_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x90)  /* trace12 config. */
#define CSR_HIPCIEC50_PCS_GLB_REG_TRACE_DATA_PORT4_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x94)  /* Trace data out */
#define CSR_HIPCIEC50_PCS_GLB_REG_TRACE_DATA_PORT8_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x98)  /* s */
#define CSR_HIPCIEC50_PCS_GLB_REG_TRACE_DATA_PORT12_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x9C) /* Trace data */
#define CSR_HIPCIEC50_PCS_GLB_REG_TRACE_CTRL_AND_ECC_0_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0xA0) /* trace0 or 4 read enable */
#define CSR_HIPCIEC50_PCS_GLB_REG_TRACE_CTRL_AND_ECC_1_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0xA4) /* trace8 or 12 read enable */
#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_INTR_STATUS_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0xA8)                                                /* PCS CE interrupt source */
#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_INTR_SET_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0xAC) /* PCS CE interrupt set */
#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_INTR_MSK_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0xB0) /* PCS CE interrupt mask */
#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_INTR_RO_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0xB4)  /* PCS CE interrupt status \
                                                                                            */
#define CSR_HIPCIEC50_PCS_GLB_REG_RX_ELECEIDLE_PRT_NUM_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0xB8) /* LOS protect cycle */
#define CSR_HIPCIEC50_PCS_GLB_REG_RX_RCV_EIOS_WIDTH_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0xBC) /* pcs2sds_rcv_eios width configuration */
#define CSR_HIPCIEC50_PCS_GLB_REG_RXVALID_PROTECNTION_PARA_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x120) /* rxvalid protect num */
#define CSR_HIPCIEC50_PCS_GLB_REG_INJECT_1BIT_ERROR_NUM_S_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x124) /* 1bit error insert times */
#define CSR_HIPCIEC50_PCS_GLB_REG_INJECT_2BIT_ERROR_NUM_S_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x128) /* 2bit error insert times */
#define CSR_HIPCIEC50_PCS_GLB_REG_INJECT_1CYCLE_ERROR_NUM_S_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x12C) /* 1 clock cycle error insert times */
#define CSR_HIPCIEC50_PCS_GLB_REG_RX_MARGIN_EN_PARA_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x130) /* rxmargin_en protect cycle */
#define CSR_HIPCIEC50_PCS_GLB_REG_RX_MARGIN_RDY_PARA_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x134)                                           /* rxmargin_rdy timeout cycle */
#define CSR_HIPCIEC50_PCS_GLB_REG_FS_CALC_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x378) /* FS average calculation */
#define CSR_HIPCIEC50_PCS_GLB_REG_FS_CALC_TIMEOUT_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x37C) /* FS average calculation timeout */
#define CSR_HIPCIEC50_PCS_GLB_REG_FS_CALC_STATUS_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x380) /* FS average calculation statue */
#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_STATUS_REN_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x384) /* all status read enable */
#define CSR_HIPCIEC50_PCS_GLB_REG_RXTX_STATUS_TIMEOUT_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x388) /* rxtx_status protect time */
#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_VERSION_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x38C)      /* PCS version */
#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_RELEASE_DATE_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x390) /* PCS release date */
#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_PORT_LINK_MODE_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x394) /* port link mode just for PCS */
#define CSR_HIPCIEC50_PCS_GLB_REG_CFG_A_LINE_L_ERR_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x398) /* Error inject line-A low 23bit */
#define CSR_HIPCIEC50_PCS_GLB_REG_CFG_B_LINE_L_ERR_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x39C) /* Error inject line-B low 23bit */
#define CSR_HIPCIEC50_PCS_GLB_REG_CFG_C_LINE_L_ERR_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x3A0) /* Error inject line-C low 23bit */
#define CSR_HIPCIEC50_PCS_GLB_REG_FS_CALC_RDY_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x3A4) /* serdes to pcs tx fs ready */
#define CSR_HIPCIEC50_PCS_GLB_REG_PMA_RXEQ_DFX_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x3A8) /* PCS to SerDes txdeemph \
                                                                                             */
#define CSR_HIPCIEC50_PCS_GLB_REG_SERDES_DFX_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x3AC) /* prbs error and cs calib done */
#define CSR_HIPCIEC50_PCS_GLB_REG_INT_TYPE_SEL_CE_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x3B0) /* pcs interrupt type selection for ce */
#define CSR_HIPCIEC50_PCS_GLB_REG_INT_TYPE_SEL_NFE_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x3B4) /* pcs interrupt type selection for nfe */
#define CSR_HIPCIEC50_PCS_GLB_REG_INT_TYPE_SEL_FE_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x3B8) /* pcs interrupt type selection for fe */
#define CSR_HIPCIEC50_PCS_GLB_REG_INT_TYPE_SEL_NI_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x3BC) /* pcs interrupt type selection for ni */
#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_INTR_NFE_STATUS_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x3C0) /* PCS NFE interrupt source */
#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_INTR_NFE_SET_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x3C4) /* PCS NFE interrupt set */
#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_INTR_NFE_MSK_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x3C8) /* PCS NFE interrupt mask */
#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_INTR_NFE_RO_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x3CC) /* PCS NFE interrupt status */
#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_INTR_FE_STATUS_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x3D0) /* PCS FE interrupt source */
#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_INTR_FE_SET_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x3D4) /* PCS FE interrupt set */
#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_INTR_FE_MSK_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x3D8) /* PCS FE interrupt mask */
#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_INTR_FE_RO_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x3DC) /* PCS FE interrupt status */
#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_INTR_NI_STATUS_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x3E0) /* PCS NI interrupt source */
#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_INTR_NI_SET_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x3E4) /* PCS NI interrupt set */
#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_INTR_NI_MSK_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x3E8) /* PCS NI interrupt mask */
#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_INTR_NI_RO_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x3EC) /* PCS NI interrupt status */
#define CSR_HIPCIEC50_PCS_GLB_REG_POWER_CHGE_PRT_MODE_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x3F4) /* power change protect mode */
#define CSR_HIPCIEC50_PCS_GLB_REG_POWER_CHGE_WAIT_IDLE_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x3F8) /* power change wait idle */
#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_CDC_DPTX_FIFO_THRES_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x3FC) /* pcs cdc module tx data path fifo thres */
#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_LANE2MACRO_MAP_0_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x400) /* pcs lane2macro mapping */
#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_LANE2MACRO_MAP_1_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x404) /* pcs lane2macro mapping */
#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_CDC_GLOBAL_STATUS0_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x408) /* pcs cdc module global status */
#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_CDC_GLOBAL_STATUS1_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x40C) /* pcs cdc module global status */
#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_CDC_GLOBAL_STATUS2_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x410) /* pcs cdc module global status */
#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_CDC_GLOBAL_STATUS3_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x414) /* pcs cdc module global status */
#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_CDC_GLOBAL_CFG_REG \
    (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x418) /* pcs cdc module global configure */
#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_CDC_SKP_TH_G1_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x41C)
#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_CDC_SKP_TH_G2_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x420)
#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_CDC_SKP_TH_G3_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x424)
#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_CDC_SKP_TH_G4_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x428)
#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_CDC_SKP_TH_G5_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x42C)
#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_CDC_SKP_PROC_EN_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x430)
#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_CDC_SKP_REQ_DLY_TH_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x434)
#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_CDC_TX_ELE_EXIT_PROTECT_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x438)
#define CSR_HIPCIEC50_PCS_GLB_REG_RETIMER_FUNCTION_SWITCH_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x43C)
#define CSR_HIPCIEC50_PCS_GLB_REG_PWRCHGE_PHYSTS_DLY_PARAM_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x440)
#define CSR_HIPCIEC50_PCS_GLB_REG_PMA_CMD_PARA_0_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x444)
#define CSR_HIPCIEC50_PCS_GLB_REG_PMA_CMD_PARA_1_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x448)
#define CSR_HIPCIEC50_PCS_GLB_REG_PMA_CMD_PARA_2_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x44C)
#define CSR_HIPCIEC50_PCS_GLB_REG_PMA_CMD_STS_0_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x450)
#define CSR_HIPCIEC50_PCS_GLB_REG_PMA_CMD_STS_1_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x454)
#define CSR_HIPCIEC50_PCS_GLB_REG_PMA_CMD_STS_2_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x458)
#define CSR_HIPCIEC50_PCS_GLB_REG_PMA_CMD_STS_3_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x45C)
#define CSR_HIPCIEC50_PCS_GLB_REG_PMA_CMD_STS_4_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x460)
#define CSR_HIPCIEC50_PCS_GLB_REG_PMA_CMD_STS_0_1_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x464)
#define CSR_HIPCIEC50_PCS_GLB_REG_PMA_CMD_STS_1_1_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x468)
#define CSR_HIPCIEC50_PCS_GLB_REG_PMA_CMD_STS_2_1_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x46C)
#define CSR_HIPCIEC50_PCS_GLB_REG_PMA_CMD_STS_3_1_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x470)
#define CSR_HIPCIEC50_PCS_GLB_REG_PMA_CMD_STS_4_1_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x474)
#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_CLK_ICG_EN_0_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x478)
#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_CLK_ICG_EN_1_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x47C)
#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_TIMER_CFG_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x480)
#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_EIOS_CLR_LOCK_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x484)
#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_SERIAL_INTVE_TIME_P0S_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x488)
#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_SERIAL_INTVE_TIME_P1_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x48C)
#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_SERIAL_INTVE_TIME_P2_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x490)
#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_SERIAL_INTVE_TIME_RXL0S_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x494)
#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_SERIAL_INTVE_TIME_MODE_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x498)
#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_SERIAL_INTVE_TIME_REFCLK_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x49C)
#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_REFCLK_STATUS_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x4A0)

/* HIPCIEC50_PCS_LANE_REG Base address of Module's Register */
#define CSR_HIPCIEC50_PCS_LANE_REG_BASE (0x5B000)

/* **************************************************************************** */
/*                      HIPCIEC50_PCS_LANE_REG Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_HIPCIEC50_PCS_LANE_REG_M_PCS_IN13_CFG_REG (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x0) /* PMA bypass config. */
#define CSR_HIPCIEC50_PCS_LANE_REG_M_PCS_IN14_CFG_REG (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x4) /* PMA bypass config. */
#define CSR_HIPCIEC50_PCS_LANE_REG_M_PCS_IN15_CFG_REG (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x8) /* PMA bypass config. */
#define CSR_HIPCIEC50_PCS_LANE_REG_MUX_LOS_ALOS_REG (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0xC)   /* PMA bypass config. */
#define CSR_HIPCIEC50_PCS_LANE_REG_SDS_CFG_REG_REG (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x10)   /* PIPE bypass config. */
#define CSR_HIPCIEC50_PCS_LANE_REG_M_PCS_RPT_REG_REG (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x14) /* rx status */
#define CSR_HIPCIEC50_PCS_LANE_REG_SERDES_STATUS_RPT_REG (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x18) /* PMA status */
#define CSR_HIPCIEC50_PCS_LANE_REG_TIME_OUT_RPT_REG (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x1C) /* skp add or rem status \
                                                                                              */
#define CSR_HIPCIEC50_PCS_LANE_REG_POLARITY_RXVALID_RXELECIDLE_REG \
    (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x20)                                                /* PIPE bypass config. */
#define CSR_HIPCIEC50_PCS_LANE_REG_STATUS_CLR_REG (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x24)  /* error counter clear */
#define CSR_HIPCIEC50_PCS_LANE_REG_EBUF_STATUS_REG (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x28) /* ebuf status */
#define CSR_HIPCIEC50_PCS_LANE_REG_GEN3_DEC_ENC_STATUS_REG \
    (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x2C)                                                /* 128B130B encode status */
#define CSR_HIPCIEC50_PCS_LANE_REG_WAKE_STATUS_REG (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x30) /* wake control status */
#define CSR_HIPCIEC50_PCS_LANE_REG_RECV_DET_OR_PWR_CHAGE_REG \
    (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x34) /* receiver detect or power change status */
#define CSR_HIPCIEC50_PCS_LANE_REG_EQEVAL_STATUS_REG (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x38) /* eyediag test status \
                                                                                               */
#define CSR_HIPCIEC50_PCS_LANE_REG_RATE_CHGE_STATUS0_REG \
    (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x3C) /* rate change status */
#define CSR_HIPCIEC50_PCS_LANE_REG_LANE_INTR_RO_REG \
    (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x40) /* PCS lane interrupt status CE */
#define CSR_HIPCIEC50_PCS_LANE_REG_LANE_INTR_SET_REG \
    (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x44) /* PCS  lane interrupt set */
#define CSR_HIPCIEC50_PCS_LANE_REG_LANE_INTR_MASK_REG \
    (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x48) /* PCS lane interrupt mask */
#define CSR_HIPCIEC50_PCS_LANE_REG_LANE_INTR_STATUS_REG \
    (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x4C) /* PCS lane interrupt source */
#define CSR_HIPCIEC50_PCS_LANE_REG_LANE_EBUF_PARA_REG \
    (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x50) /* PCS lane elbuf water line */
#define CSR_HIPCIEC50_PCS_LANE_REG_RX_MARGIN_STATUS_REG (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x54) /* RXMARGIN status */
#define CSR_HIPCIEC50_PCS_LANE_REG_RX_MARGIN_TIMEOUT_REG \
    (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x58) /* RXMARGIN timeout counter */
#define CSR_HIPCIEC50_PCS_LANE_REG_RXEQ_COARSETUNE_TIMEOUT_REG \
    (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x5C) /* coarsetune timeout counter */
#define CSR_HIPCIEC50_PCS_LANE_REG_RXEQ_FINETUNE_TIMEOUT_REG \
    (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x60) /* finetune timeout counter */
#define CSR_HIPCIEC50_PCS_LANE_REG_DETECT_CLK_FLG_REG \
    (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x64) /* dfx tx/rxclk exist flag */
#define CSR_HIPCIEC50_PCS_LANE_REG_MSG_BUS_DFX_REG (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x68) /* message bus fsm state \
                                                                                             */
#define CSR_HIPCIEC50_PCS_LANE_REG_RXEQ_START_CTRL_REG \
    (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x6C) /* PCS to SERDES rxeq control */
#define CSR_HIPCIEC50_PCS_LANE_REG_LANE_INTR_RO_NFE_REG \
    (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x70) /* PCS lane interrupt status NFE */
#define CSR_HIPCIEC50_PCS_LANE_REG_LANE_INTR_RO_FE_REG \
    (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x74) /* PCS lane interrupt status FE */
#define CSR_HIPCIEC50_PCS_LANE_REG_LANE_INTR_RO_NI_REG \
    (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x78) /* PCS lane interrupt status NI */
#define CSR_HIPCIEC50_PCS_LANE_REG_PHY2MAC_MSG_STATUS_REG \
    (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x7C) /* phy2mac message bus status */
#define CSR_HIPCIEC50_PCS_LANE_REG_PCS_MSG_PIN_EN_REG (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x800) /* message bus status \
                                                                                                 */
#define CSR_HIPCIEC50_PCS_LANE_REG_PCS_MSG_TIME_PROTECT_REG \
    (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x804) /* message bus timeout para */
#define CSR_HIPCIEC50_PCS_LANE_REG_TXBEACON_RXL0S_TIMEOUT_REG \
    (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x808) /* rxl0s and txbeacon timeout para */
#define CSR_HIPCIEC50_PCS_LANE_REG_PCS_MISC_CTRL_PARA_0_REG \
    (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x80C) /* misc ctrl signal */
#define CSR_HIPCIEC50_PCS_LANE_REG_PCS_BEACON_RXL0S_STATUS_REG \
    (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x810) /* beacon and rxl0s status */
#define CSR_HIPCIEC50_PCS_LANE_REG_PCS_CDC_LANE_STATUS0_REG \
    (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x814) /* pcs cdc module lane status */
#define CSR_HIPCIEC50_PCS_LANE_REG_PCS_CDC_LANE_STATUS1_REG \
    (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x818) /* pcs cdc module lane status */
#define CSR_HIPCIEC50_PCS_LANE_REG_PCS_CDC_LANE_STATUS2_REG \
    (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x81C) /* pcs cdc module lane status */
#define CSR_HIPCIEC50_PCS_LANE_REG_PCS_CDC_LANE_STATUS3_REG \
    (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x820) /* pcs cdc module lane status */
#define CSR_HIPCIEC50_PCS_LANE_REG_PCS_RXTX_STATUS_IN_LOW_REG \
    (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x824) /* rxtx-status stay in low time */
#define CSR_HIPCIEC50_PCS_LANE_REG_PCS_PWRCHGE_CNT_REG \
    (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x828) /* the time of power change in PIPE */

#endif
